1. Technical Field
The present invention relates to data processing systems in general, and in particular to symmetric multiprocessor systems. Still more particularly, the present invention relates to a method and apparatus for transmitting packets among processing nodes within a symmetric multiprocessor system.
2. Description of the Prior Art
It is well-known in the computer arts that greater processing performance can be achieved by harnessing the processing power of multiple individual processors in tandem. Multiprocessor computer systems can be designed with a number of different architectures, of which one may be better suited for a particular application over the others, depending upon the intended design, system performance requirements, and software environment. Known multiprocessor architectures include, for example, symmetric multiprocessor (SNP) system architecture and non-uniform memory access (NUMA) system architecture.
In an SMP data processing system, all of the processing units are generally identical; that is, they all have the same architecture and utilize a common set or subset of instructions and protocols to operate. Typically, each processing unit includes a processor core having at least one execution unit for carrying out program instructions. In addition, each processing unit may include at least one level of caches, commonly referred to as level one (L1) caches, which are typically implemented with high-speed memories. Similarly, a second level of caches, commonly referred to as level two (L2) caches, may also be included in each processing unit for supporting the L1 caches. Sometimes, a third level of caches, commonly referred to as level three (L3) caches, may also be included in each processing unit for supporting the L2 caches. Each level of caches stores a subset of the data and/or instructions contained in a system memory for low-latency accesses by various processor cores.
The present disclosure describes a method and apparatus for transmitting packets among various processing nodes within an SMP system.